Developed cascaded multilevel inverter topology to minimise the number of circuit devices and voltage stresses of switches
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چکیده
منابع مشابه
Reduction the Number of Power Electronic Devices of a Cascaded Multilevel Inverter Based on New General Topology
In this paper, a new cascaded multilevel inverter by capability of increasing the number of output voltage levels with reduced number of power switches is proposed. The proposed topology consists of series connection of a number of proposed basic multilevel units. In order to generate all voltage levels at the output, five different algorithms are proposed to determine the magnitude of DC volta...
متن کاملreduction the number of power electronic devices of a cascaded multilevel inverter based on new general topology
in this paper, a new cascaded multilevel inverter by capability of increasing the number of output voltage levels with reduced number of power switches is proposed. the proposed topology consists of series connection of a number of proposed basic multilevel units. in order to generate all voltage levels at the output, five different algorithms are proposed to determine the magnitude of dc volta...
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In this paper, several optimum structures of a cascaded multilevel inverter is proposed. This optimization is based on generation a constant number of output voltage levels by using minimum number of power switches or dc voltage sources or minimum amount of blocked voltage by power switches. In addition, the optimum structure for a constant number of dc voltage sources by using minimum number o...
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In this paper, a new topology of cascaded multilevel inverter using a reduced number of switches is proposed. The new topology has the advantage of reduced number devices compared to traditional configurations and can be extended to any number of levels. This topology results in reduction of installation area, cost, computational time and has simplicity of control system. This structure consist...
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In this paper, a new configuration for symmetrical and asymmetrical multilevel inverters is proposed. In asymmetric mode, different algorithms are suggested in order to determine the magnitudes of DC voltage sources. The merit of this topology to the conventional symmetric and asymmetric inverters is verified by the provided comparisons. This topology uses a lower number of power electronic dev...
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ژورنال
عنوان ژورنال: IET Power Electronics
سال: 2014
ISSN: 1755-4543,1755-4543
DOI: 10.1049/iet-pel.2013.0080